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cy7c1441av33 CY7C1443AV33, cy7c1447av33 36-mbit (1 m 36/2 m 18/512 k 72) flow-through sram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-05357 rev. *i revised may 23, 2011 36-mbit (1 m 36/2 m 18/512 k 72) flow-through sram features supports 133-mhz bus operations 1 m 36/2 m 18/512 k 72 common io 3.3 v core power supply 2.5 v or 3.3 v io power supply fast clock-to-output times ? 6.5 ns (133-mhz version) provide high-performance 2-1-1-1 access rate user-selectable burst counter supporting intel ? pentium ? interleaved or linear burst sequences separate processor and controller address strobes synchronous self-timed write asynchronous output enable cy7c1441av33, CY7C1443AV33 available in jedec-standard pb-free 100-pin tqfp package, pb-free and non pb-free 165-ball fbga package. cy7c1447av33 available in pb-free and non pb-free 209-ball fbga package ieee 1149.1 jtag-compatible boundary scan ?zz? sleep mode option functional description the cy7c1441av33/CY7C1443AV33/cy7c1447av33 [1] are 3.3 v, 1 m 36/2 m 18/512 k 72 synchronous flow-through srams, respectively designed to interface with high-speed microprocessors with minimum glue logic. maximum access delay from clock rise is 6.5 ns (133-mhz version). a 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the re st of the burst access. all synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (clk). the synchronous inputs include all addresses, all data inputs, address-pipelining chip enable (ce 1 ), depth-expansion chip enables (ce 2 and ce 3 ), burst control inputs (adsc , adsp , and adv ), write enables (bw x , and bwe ), and global write (gw ). asynchronous inputs include the output enable (oe ) and the zz pin. the cy7c1441av33/CY7C1443AV33/cy7c1447av33 allows either interleaved or linear burst sequences, selected by the mode input pin. a high selects an interleaved burst sequence, while a low selects a linear bu rst sequence. burst accesses can be initiated with the processor address strobe (adsp ) or the cache controller address strobe (adsc ) inputs. address advancement is controlled by the address advancement (adv ) input. addresses and chip enables are registered at rising edge of clock when either address strobe processor (adsp ) or address strobe controller (adsc ) are active. subsequent burst addresses can be internally generated as controlled by the advance pin (adv ). the cy7c1441av33/CY7C1443AV33/cy7c1447av33 operates from a +3.3 v core power supply while all outputs may operate with either a +2.5 or +3.3 v supply. all inputs and outputs are jedec-standard jesd8-5-compatible. selection guide description 133 mhz 100 mhz unit maximum access time 6.5 8.5 ns maximum operating current 310 290 ma maximum cmos standby current 120 120 ma note 1. for best-practices recommendations, pleas e refer to the cypress application note system design guidelines on www.cypress.com . [+] feedback
cy7c1441av33 CY7C1443AV33, cy7c1447av33 document number: 38-05357 rev. *i page 2 of 34 logic block diagram ? cy7c1441av33 (1 m 36) logic block diagram ? CY7C1443AV33 (2 m 18) address register burst counter and logic clr q1 q0 enable register sense amps output buffers input registers memory array mode a [1:0] zz dq s dqp a dqp b dqp c dqp d a 0, a1, a adv clk adsp adsc bw d bw c bw b bw a bwe ce1 ce2 ce3 oe gw sleep control dq a , dqp a byte write register dq b , dqp b byte write register dq c , dqp c byte write register byte write register dq d , dqp d byte write register dq d , dqp d byte write register dq c , dqp c byte write register dq b , dqp b byte write register dq a , dqp a byte write register address register adv clk burst counter and logic clr q1 q0 adsc ce 1 oe sense amps memory array adsp output buffers input registers mode ce 2 ce 3 gw bwe a 0,a1,a bw b bw a dq b ,dqp b write register dq a ,dqp a write register enable register a[1:0] dqs dqp a dqp b dq b ,dqp b write driver dq a ,dqp a write driver sleep control zz [+] feedback
cy7c1441av33 CY7C1443AV33, cy7c1447av33 document number: 38-05357 rev. *i page 3 of 34 logic block diagram ? cy7c1447av33 (512 k 72) bw d bw c bw b bw a bwe gw ce1 ce2 ce3 oe enable register address register adv clk burst counter and logic clr q1 q0 adsp adsc mode a 0, a1,a a[1:0] bw f bw e bw h bw g output buffers dq a , dqp a write driver dq b , dqp b write driver dq c , dqp c write driver dq d , dqp d write driver byte a write driver dq e , dqp e write driver dq f , dqp f write driver dq g , dqp g write driver dq h , dqp h write driver memory array sense amps sleep control zz input registers dqs dqp a dqp b dqp c dqp d dqp e dqp f dqp g dqp h dq a , dqp a write register dq b , dqp b write register dq c , dqp c write register dq d , dqp d write register dq e , dqp e write register dq f , dqp f write register dq f , dqp f write register dq h , dqp h write register [+] feedback
cy7c1441av33 CY7C1443AV33, cy7c1447av33 document number: 38-05357 rev. *i page 4 of 34 contents pin configurations ........................................................... 5 pin definitions .................................................................. 8 functional overview ...................................................... 10 single read accesses .............................................. 10 single write accesse s initiated by adsp ................. 10 single write accesses initiated by adsc ................. 10 burst sequences ....................................................... 10 sleep mode ............................................................... 10 interleaved burst address table (mode = floating or vdd) ............................................. 10 linear burst address table (mode = gnd) ................ 10 zz mode electrical characteristics ............................... 11 truth table ...................................................................... 11 partial truth table for read/write ................................ 12 truth table for read/write ............................................ 12 truth table for read/write ............................................ 12 ieee 1149.1 serial boundary sc an (jtag) ... ........... .... 13 disabling the jtag feature ...................................... 13 tap controller state diagram ....................................... 13 test access port (tap) ............................................. 13 tap controller block diagram ...................................... 13 performing a tap r eset .......... .............. .......... 13 tap registers ...................................................... 13 tap instruction set ................................................... 14 tap timing ...................................................................... 15 tap ac switching characteristics ............................... 16 3.3 v tap ac test conditions ....................................... 17 3.3 v tap ac output load equivalent ......................... 17 2.5 v tap ac test conditions ....................................... 17 2.5v tap ac output load equivalent .......................... 17 tap dc electrical characteristics and operating conditions ..................................................... 17 identification register definitions ................................ 18 scan register sizes ....................................................... 18 identification codes ....................................................... 18 165-ball fbga boundary scan order ........................... 19 maximum ratings ........................................................... 20 operating range ............................................................. 20 electrical characteristics ............................................... 20 dc electrical characteristics ..................................... 20 capacitance .................................................................... 21 parameter ........................................................................ 21 thermal resistance ........................................................ 21 switching characteristics .............................................. 22 timing diagrams ............................................................ 23 ordering information ...................................................... 27 ordering code definitions ..... .................................... 27 package diagrams .......................................................... 28 acronyms ........................................................................ 31 document conventions ................................................. 31 units of measure ....................................................... 31 document history page ................................................. 32 sales, solutions, and legal information ...................... 34 worldwide sales and design s upport ......... .............. 34 products .................................................................... 34 psoc solutions ......................................................... 34 [+] feedback
cy7c1441av33 CY7C1443AV33, cy7c1447av33 document number: 38-05357 rev. *i page 5 of 34 pin configurations figure 1. 100-pin tqfp pinout a a a a a 1 a 0 nc/72m a v ss v dd a a a a a a a a dqp b dq b dq b v ddq v ssq dq b dq b dq b dq b v ssq v ddq dq b dq b v ss nc v dd zz dq a dq a v ddq v ssq dq a dq a dq a dq a v ssq v ddq dq a dq a dqp a dqp c dq c dq c v ddq v ssq dq c dq c dq c dq c v ssq v ddq dq c dq c v dd nc v ss dq d dq d v ddq v ssq dq d dq d dq d dq d v ssq v ddq dq d dq d dqp d a a ce 1 ce 2 bw d bw c bw b bw a ce 3 v dd v ss clk gw bwe oe adsc adsp adv a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 mode cy7c1441av33 (1 m 36) nc a a a a a 1 a 0 nc/72m a v ss v dd a a a a a a a a a nc nc v ddq v ssq nc dqp a dq a dq a v ssq v ddq dq a dq a v ss nc v dd zz dq a dq a v ddq v ssq dq a dq a nc nc v ssq v ddq nc nc nc nc nc nc v ddq v ssq nc nc dq b dq b v ssq v ddq dq b dq b v dd nc v ss dq b dq b v ddq v ssq dq b dq b dqp b nc v ssq v ddq nc nc nc a a ce 1 ce 2 nc nc bw b bw a ce 3 v dd v ss clk gw bwe oe adsc adsp adv a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 mode CY7C1443AV33 (2 m 18) nc a a [+] feedback
cy7c1441av33 CY7C1443AV33, cy7c1447av33 document number: 38-05357 rev. *i page 6 of 34 pin configurations (continued) 165-ball fbga (15 17 1.4 mm) pinout cy7c1441av33 (1 m 36) 234 567 1 a b c d e f g h j k l m n p r tdo nc/288m nc/144m dqp c dq c dqp d nc dq d ce 1 bw b ce 3 bw c bwe a ce 2 dq c dq d dq d mode nc dq c dq c dq d dq d dq d a nc/72m v ddq bw d bw a clk gw v ss v ss v ss v ss v ddq v ss v dd v ss v ss v ss v ss v ss v ss v ddq v ddq nc v ddq v ddq v ddq v ddq a a v dd v ss v dd v ss v ss v ddq v dd v ss v dd v ss v dd v ss v ss v ss v dd v dd v ss v dd v ss v ss nc tck v ss tdi a a dq c v ss dq c v ss dq c dq c nc v ss v ss v ss v ss nc v ss a1 dq d dq d nc nc v ddq v ss tms 891011 a adv a adsc nc oe adsp a nc/576m v ss v ddq nc/1g dqp b v ddq v dd dq b dq b dq b nc dq b nc dq a dq a v dd v ddq v dd v ddq dq b v dd nc v dd dq a v dd v ddq dq a v ddq v dd v dd v ddq v dd v ddq dq a v ddq a a v ss a a a dq b dq b dq b zz dq a dq a dqp a dq a a v ddq a CY7C1443AV33 (2 m 18) a0 a v ss 234 567 1 a b c d e f g h j k l m n p r tdo nc/288m nc/144m nc nc dqp b nc dq b ace 1 nc ce 3 bw b bwe a ce 2 nc dq b dq b mode nc dq b dq b nc nc nc a nc/72m v ddq nc bw a clk gw v ss v ss v ss v ss v ddq v ss v dd v ss v ss v ss v ss v ss v ss v ss v ddq v ddq nc v ddq v ddq v ddq v ddq a a v dd v ss v dd v ss v ss v ddq v dd v ss v dd v ss v dd v ss v ss v ss v dd v dd v ss v dd v ss v ss nc tck a0 v ss tdi a a dq b v ss nc v ss dq b nc nc v ss v ss v ss v ss nc v ss a1 dq b nc nc nc v ddq v ss tms 891011 a adv a adsc a oe adsp a nc/576m v ss v ddq nc/1g dqp a v ddq v dd nc dq a dq a nc nc nc dq a nc v dd v ddq v dd v ddq dq a v dd nc v dd nc v dd v ddq dq a v ddq v dd v dd v ddq v dd v ddq nc v ddq a a v ss a a a dq a nc nc zz dq a nc nc dq a a v ddq a a a [+] feedback
cy7c1441av33 CY7C1443AV33, cy7c1447av33 document number: 38-05357 rev. *i page 7 of 34 pin configurations (continued) a b c d e f g h j k l m n p r t u v w 123456789 11 10 dq g dq g dq g dq g dq g dq g dq g dq g dq c dq c dq c dq c nc dqp g dq h dq h dq h dq h dq d dq d dq d dq d dqp d dqp c dq c dq c dq c dq c nc dq h dq h dq h dq h dqp h dq d dq d dq d dq d dq b dq b dq b dq b dq b dq b dq b dq b dq f dq f dq f dq f nc dqp f dq a dq a dq a dq a dq e dq e dq e dq e dqp a dqp b dq f dq f dq f dq f nc dq a dq a dq a dq a dqp e dq e dq e dq e dq e a adsp adv a nc nc nc/72m aa a a aa aa a a1 a0 a aa aa a nc/144m nc288m nc/576m gw nc nc bws b bws f bws e bws a bws c bws g bws d bws h tms tdi tdo tck nc nc mode nc v ss v ss nc clk nc v ss v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v ss v ss v ss v ss v ss v ss v ss v ss nc/1g v dd nc oe ce 3 ce 1 ce 2 adsc bw v ss v ss v ss v ss v ss v ss v ss zz v ss v ss v ss v ss nc v ddq v ss v ss nc v ss v ss v ss v ss v ss v ss nc v ss v ddq v ddq v ddq v ddq v ddq nc v ddq v ddq v ddq v ddq nc v ddq v ddq v ddq v ddq nc v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq 209-ball fbga (14 22 1.76 mm) pinout cy7c1447av33 (512 k 72) [+] feedback
cy7c1441av33 CY7C1443AV33, cy7c1447av33 document number: 38-05357 rev. *i page 8 of 34 pin definitions name io description a 0 , a 1 , a input- synchronous address inputs used to select one of the address location s. sampled at the rising edge of the clk if adsp or adsc is active low, and ce 1 , ce 2 , and ce 3 are sampled active. a [1:0] feed the 2-bit counter. bw a , bw b , bw c , bw d , bw e , bw f , bw g , bw h input- synchronous byte write select inputs, active low . qualified with bwe to conduct byte writes to the sram. sampled on the rising edge of clk. gw input- synchronous global write enable input, active low . when asserted low on the rising edge of clk, a global write is conducted (all bytes are written, regardless of the values on bw x and bwe ). clk input- clock clock input . used to capture all synchronous inputs to the device. also used to increment the burst counter when adv is asserted low, during a burst operation. ce 1 input- synchronous chip enable 1 input, active low . sampled on the rising edge of clk. used in conjunction with ce 2 and ce 3 to select/deselect the device. adsp is ignored if ce 1 is high. ce 1 is sampled only when a new external address is loaded. ce 2 input- synchronous chip enable 2 input, active high . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 3 to select/deselect the device. ce 2 is sampled only when a new external address is loaded. ce 3 input- synchronous chip enable 3 input, active low . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 2 to select/deselect the device. ce 3 is assumed active throughout this document for bga. ce 3 is sampled only when a new external address is loaded. oe input- asynchronous output enable, asynchronous input, active low . controls the direction of the io pins. when low, the io pins behave as outputs. when dea sserted high, io pins are tri-stated, and act as input data pins. oe is masked during the first clock of a read cycle when emerging from a deselected state. adv input- synchronous advance input signal, sampled on the rising edge of clk . when asserted, it automatically increments the address in a burst cycle. adsp input- synchronous address strobe from processor, sampled on the rising edge of clk, active low . when asserted low, addresses presented to the devi ce are captured in the address registers. a [1:0] are also loaded into the burst counter. when adsp and adsc are both asserted, only adsp is recognized. asdp is ignored when ce 1 is deasserted high adsc input- synchronous address strobe from controller, sampled on the rising edge of clk, active low . when asserted low, addresses presented to the devi ce are captured in the address registers. a [1:0] are also loaded into the burst counter. when adsp and adsc are both asserted, only adsp is recognized . bwe input- synchronous byte write enable input, active low . sampled on the rising edge of clk. this signal must be asserted low to conduct a byte write. zz input- asynchronous zz ?sleep? input, active high . when asserted high places the device in a non-time-critical ?sleep? condition with data integrity preserved. for normal operation, this pin must be low or left floating. zz pin has an internal pull down. dq s io- synchronous bidirectional data io lines . as inputs, they feed into an on-ch ip data register that is triggered by the rising edge of clk. as outputs, they deliver the data contained in the memory location specified by the addresses presented during the pr evious clock rise of the read cycle. the direction of the pins is controlled by oe . when oe is asserted low, the pins behave as outputs. when high, dq s and dqp x are placed in a tri-state condi tion.the outputs are automatically tri-stated during the data portion of a write se quence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of oe . dqp x io- synchronous bidirectional data parity io lines. functionally, these signals are identical to dq s . during write sequences, dqp x is controlled by bw [a:h] correspondingly. mode input-static selects burst order . when tied to gnd selects linear burst sequence. when tied to v dd or left floating selects interleaved burst sequence. this is a strap pin and should remain static during device operation. mode pin has an internal pull up. [+] feedback
cy7c1441av33 CY7C1443AV33, cy7c1447av33 document number: 38-05357 rev. *i page 9 of 34 v dd power supply power supply inputs to the core of the device . v ddq io power supply power supply for the io circuitry . v ss ground ground for the core of the device . v ssq io ground ground for the io circuitry . tdo jtag serial output synchronous serial data-out to the jtag circuit . delivers data on the negativ e edge of tck. if the jtag feature is not being utilized, this pin should be le ft unconnected. this pin is not available on tqfp packages. tdi jtag serial input synchronous serial data-in to the jtag circuit . sampled on the rising edge of tck. if the jtag feature is not being utilized, this pin can be left floating or connected to v dd through a pull up resistor. this pin is not available on tqfp packages. tms jtag serial input synchronous serial data-in to the jtag circuit . sampled on the rising edge of tck. if the jtag feature is not being utilized, this pin can be disconnected or connected to v dd . this pin is not available on tqfp packages. tck jtag-clock clock input to th e jtag circuitry . if the jtag feature is not being utilized, this pin must be connected to v ss . this pin is not available on tqfp packages. nc - no connects . not internally connected to the die. 72m, 144m and 288m are address expansion pins are not internally connected to the die. nc/72m, nc/144m, nc/288m, nc/576m, nc/1g - no connects . not internally connected to the di e. nc/72m, nc/144m, nc/288m, nc/576m and nc/1g are address expansion pins are not internally connected to the die. pin definitions (continued) name io description [+] feedback
cy7c1441av33 CY7C1443AV33, cy7c1447av33 document number: 38-05357 rev. *i page 10 of 34 functional overview all synchronous inputs pass through input registers controlled by the rising edge of the clock. maximum access delay from the clock rise (t cdv ) is 6.5 ns (133-mhz device). the cy7c1441av33/CY7C1443AV33/cy7c1447av33 supports secondary cache in syst ems utilizing either a linear or interleaved burst sequence. the interleaved burst order supports pentium and i486? processors. the linear burst sequence is suited for processo rs that utilize a linear burst sequence. the burst order is user-selectable, and is determined by sampling the mode input. accesses can be initiated with either the processor address strobe (adsp ) or the controller address strobe (adsc ). address advancement through the burst sequence is controlled by the adv input. a two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. byte write operations are qualif ied with the byte write enable (bwe ) and byte write select (bw x ) inputs. a global write enable (gw ) overrides all byte write inputs and writes data to all four bytes. all writes are simplified with on-chip synchronous self-timed write circuitry. three synchronous chip selects (ce 1 , ce 2 , ce 3 ) and an asynchronous output enable (oe ) provide for easy bank selection and output tri-state control. adsp is ignored if ce 1 is high. single read accesses a single read access is initiated when the following conditions are satisfied at clock rise: (1) ce 1 , ce 2 , and ce 3 are all asserted active, and (2) adsp or adsc is asserted low (if the access is initiated by adsc , the write inputs must be deasserted during this first cycle). the address presented to the address inputs is latched into the address regist er and the burst counter/control logic and presented to the memory core. if the oe input is asserted low, the requested data is available at the data outputs a maximum to t cdv after clock rise. adsp is ignored if ce 1 is high. single write accesses initiated by adsp this access is initiated when the following conditions are satisfied at clock rise: (1) ce 1 , ce 2 , ce 3 are all asserted active, and (2) adsp is asserted low. the addresses presented are loaded into the address register and the burst inputs (gw , bwe , and bw x )are ignored during this first clock cycle. if the write inputs are asserted active (see write cycle descriptions table for appropriate states that indicate a write) on the next clock rise, the appropriate data is latched and written into the device. byte writes are allowed. all ios are tr i-stated during a byte write.since this is a common io device, the asynchronous oe input signal must be deasserted and the ios must be tri-stated prior to the presentation of data to dqs. as a safety precaution, the data lines are tri-stated once a write cycle is detected, regardless of the state of oe . single write accesses initiated by adsc this write access is initiated when the following conditions are satisfied at clock rise: (1) ce 1 , ce 2 , and ce 3 are all asserted active, (2) adsc is asserted low, (3) adsp is deasserted high, and (4) the write input signals (gw , bwe , and bw x ) indicate a write access. adsc is ignored if adsp is active low. the addresses presented are loaded into the address register and the burst counter/control logic and delivered to the memory core. the information presented to dq s is written into the specified address location. byte writes are allowed. all ios are tri-stated when a write is detected, even a byte write. since this is a common io device, the asynchronous oe input signal must be deasserted and the ios must be tri-stated prior to the presen- tation of data to dqs. as a safety precaution, the data lines are tri-stated once a write cycle is dete cted, regardless of the state of oe . burst sequences the cy7c1441av33/CY7C1443AV33/cy7c1447av33 provides an on-chip two-bit wraparound burst counter inside the sram. the burst counter is fed by a [1:0] , and can follow either a linear or interleaved burst order. the burst order is determined by the state of the mode input. a low on mode selects a linear burst sequence. a high on mode selects an interleaved burst order. leaving mode unconnected causes the device to default to a interleaved burst sequence. sleep mode the zz input pin is an asynchronous input. asserting zz places the sram in a power conservation ?sleep? mode. two clock cycles are required to enter into or exit from this ?sleep? mode. while in this mode, data inte grity is guaranteed. accesses pending when entering the ?sleep? mode are not considered valid nor is the completion of the operation guaranteed. the device must be deselected prior to entering the ?sleep? mode. ce 1 , ce 2 , ce 3 , adsp , and adsc must remain inactive for the duration of t zzrec after the zz input returns low. interleaved burst address table (mode = floating or v dd ) first address a1: a0 second address a1: a0 third address a1: a0 fourth address a1: a0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 linear burst address table (mode = gnd) first address a1: a0 second address a1: a0 third address a1: a0 fourth address a1: a0 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 [+] feedback
cy7c1441av33 CY7C1443AV33, cy7c1447av33 document number: 38-05357 rev. *i page 11 of 34 zz mode electrical characteristics parameter description test conditions min max unit i ddzz sleep mode standby current zz > v dd ? ? 0.2 v ? 100 ma t zzs device operation to zz zz > v dd ? 0.2 v ? 2t cyc ns t zzrec zz recovery time zz < 0.2 v 2t cyc ?ns t zzi zz active to sleep curren t this parameter is sampled ? 2t cyc ns t rzzi zz inactive to exit sleep curre nt this parameter is sampled 0 ? ns truth table tthe truth table for cy7c1441av33/CY7C1443AV33/cy7c1447av33 follows. [2, 3, 4, 5, 6] cycle description address used ce 1 ce 2 ce 3 zz adsp adsc adv write oe clk dq deselected cycle, power down none h x x l x l x x x l?h tri-state deselected cycle, power down none l l x l l x x x x l?h tri-state deselected cycle, power down none l x h l l x x x x l?h tri-state deselected cycle, power down none l l x l h l x x x l?h tri-state deselected cycle, power down none x x x l h l x x x l?h tri-state sleep mode, power down none x x x h x x x x x x tri-state read cycle, begin burst external l h l l l x x x l l?h q read cycle, begin burst external l h l l l x x x h l?h tri-state write cycle, begin burst external l h l l h l x l x l?h d read cycle, begin burst external l h l l h l x h l l?h q read cycle, begin burst external l h l l h l x h h l?h tri-state read cycle, continue burst next x x x l h h l h l l?h q read cycle, continue burst next x x x l h h l h h l?h tri-state read cycle, continue burst next h x x l x h l h l l?h q read cycle, continue burst next h x x l x h l h h l?h tri-state write cycle, continue burst next x x x l h h l l x l?h d write cycle, continue burst next h x x l x h l l x l?h d read cycle, suspend burst current x x x l h h h h l l?h q read cycle, suspend burst current x x x l h h h h h l?h tri-state read cycle, suspend burst current h x x l x h h h l l?h q read cycle, suspend burst current h x x l x h h h h l?h tri-state write cycle, suspend burst current x x x l h h h l x l?h d write cycle, suspend burst current h x x l x h h l x l?h d notes 2. x = ?don't care.? h = logic high, l = logic low. 3. write = l when any one or more byte write enable signals and bwe = l or gw = l. write = h when all byte write enable signals, bwe , gw = h. 4. the dq pins are controlled by the current cycle and the oe signal. oe is asynchronous and is not sampled with the clock. 5. the sram always initiates a read cycle when adsp is asserted, regardless of the state of gw , bwe , or bw x . writes may occur only on subsequent clocks after the adsp or with the assertion of adsc . as a result, oe must be driven high prior to the start of the write cycle to allow the outputs to tri-state. oe is a don't care for the remainder of the write cycle. 6. oe is asynchronous and is not sampled with the clock rise. it is masked internally during write cycles. during a read cycle all d ata bits are tri-state when oe is inactive or when the device is deselected, and all data bits behave as output when oe is active (low). [+] feedback
cy7c1441av33 CY7C1443AV33, cy7c1447av33 document number: 38-05357 rev. *i page 12 of 34 partial truth table for read/write function (cy7c1441av33) [7, 8] gw bwe bw d bw c bw b bw a read h h x x x x read hlhhhh write byte a (dq a , dqp a ) hlhhhl write byte b(dq b , dqp b )hlhhlh write bytes a, b (dq a , dq b , dqp a , dqp b )hlhhll write byte c (dq c , dqp c ) hlhlhh write bytes c, a (dq c , dq a, dqp c , dqp a ) hlhlhl write bytes c, b (dq c , dq b, dqp c , dqp b )hlhllh write bytes c, b, a (dq c , dq b , dq a, dqp c , dqp b , dqp a )hlhlll write byte d (dq d , dqp d ) hl lhhh write bytes d, a (dq d , dq a, dqp d , dqp a )hllhhl write bytes d, b (dq d , dq a, dqp d , dqp a )hllhlh write bytes d, b, a (dq d , dq b , dq a, dqp d , dqp b , dqp a )hllhll write bytes d, b (dq d , dq b, dqp d , dqp b ) hlllhh write bytes d, b, a (dq d , dq c , dq a, dqp d , dqp c , dqp a ) hlllhl write bytes d, c, a (dq d , dq b , dq a, dqp d , dqp b , dqp a ) hllllh write all bytes h l l l l l write all bytes l x x x x x truth table for read/write function (CY7C1443AV33) [7] gw bwe bw b bw a read h h x x read h l h h write byte a - (dq a and dqp a )hlhl write byte b - (dq b and dqp b )hllh write all bytes h l l l write all bytes l x x x truth table for read/write function (cy7c1447av33) [7, 9] gw bwe bw x read h h x read h l all bw = h write byte x ? (dq x and dqp x )hll write all bytes h l all bw = l write all bytes l x x notes 7. x = ?don't care.? h = logic high, l = logic low. 8. table only lists a partial listing of the byte write combinations. any combination of bw x is valid appropriate write is done based on which byte write is active. 9. bw x represents any byte write signal bw [a..h] .to enable any byte write bw x, a logic low signal should be applied at cloc k rise.any number of bye writes can be enabled at the same time for any given write. [+] feedback
cy7c1441av33 CY7C1443AV33, cy7c1447av33 document number: 38-05357 rev. *i page 13 of 34 ieee 1149.1 serial boundary scan (jtag) the cy7c1441av33/CY7C1443AV33/cy7c1447av33 incorporates a serial boundary scan test access port (tap). this part is fully compliant with 1149.1. the tap operates using jedec-standard 3.3 v or 2.5 v io logic levels. the cy7c1441av33/CY7C1443AV33/cy7c1447av33 contains a tap controller, instruction register, boundary scan register, bypass register, and id register. disabling the jtag feature it is possible to operate the sram without using the jtag feature. to disable the tap co ntroller, tck must be tied low (v ss ) to prevent clocking of the device. tdi and tms are internally pulled up and may be unconnected. they may alternately be connected to v dd through a pull up resistor. tdo should be left unconnected. upon power up, the device comes up in a reset state which does not interfere with the operation of the device. the 0/1 next to each state represents the value of tms at the rising edge of tck. test access port (tap) test clock (tck) the test clock is used only with the tap controller. all inputs are captured on the rising edge of tc k. all outputs are driven from the falling edge of tck. test mode select (tms) the tms input is used to give commands to the tap controller and is sampled on the rising edge of tck. it is allowable to leave this ball unconnected if the tap is not used. the ball is pulled up internally, resulting in a logic high level. test data-in (tdi) the tdi ball is used to serially in put information into the registers and can be connected to the inpu t of any of the registers. the register between tdi and tdo is chosen by the instruction that is loaded into the tap instruction register. tdi is internally pulled up and can be unconnected if the tap is unused in an application. tdi is connected to the most significant bit (msb) of any register. (see tap controller block diagram .) test data-out (tdo) the tdo output ball is used to serially clock data-out from the registers. the output is active depending upon the current state of the tap state machine. the output changes on the falling edge of tck. tdo is connected to the least significant bit (lsb) of any register. (see tap controller state diagram .) performing a tap reset a reset is performed by forcing tms high (vdd) for five rising edges of tck. this reset does not affect the operation of the sram and may be performed while the sram is operating. at power up, the tap is reset internally to ensure that tdo comes up in a high z state. tap registers registers are connected betw een the tdi and tdo balls and scan data into and out of the sram test circuitry. only one register can be selected at a time through the instruction register. data is serially loaded into the tdi ball on the rising edge of tck. data is output on the tdo ball on the falling edge of tck. tap controller state diagram test-logic reset run-test/ idle select dr-scan select ir-scan capture-dr shift-dr capture-ir shift-ir exit1-dr pause-dr exit1-ir pause-ir exit2-dr update-dr exit2-ir update-ir 1 1 1 0 1 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 tap controller block diagra bypass register 0 instruction register 0 1 2 identication register 0 1 2 29 30 31 . . . boundary scan register 0 1 2 . . x . . . selection circuitry tck tms tap controller tdi tdo selection circuitry [+] feedback
cy7c1441av33 CY7C1443AV33, cy7c1447av33 document number: 38-05357 rev. *i page 14 of 34 instruction register three-bit instructions can be seri ally loaded into the instruction register. this register is loaded when it is placed between the tdi and tdo balls as shown in the tap controller block diagram on page 13 . upon power up, the instruction register is loaded with the idcode instruction. it is also loaded with the idcode instruction if the controller is pl aced in a reset state as described in the previous section. when the tap controller is in t he capture-ir state, the two least significant bits are loaded with a binary ?01? pattern to allow for fault isolation of the board-le vel serial test data path. bypass register to save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. the bypass register is a single-bit register that can be placed between the tdi and tdo balls. this shifts data through the sram with minimal delay. the bypass register is set low (v ss ) when the bypass instruction is executed. boundary scan register the boundary scan register is connected to all the input and bidirectional balls on the sram. the boundary scan register is lo aded with the contents of the ram io ring when the tap controller is in the capture-dr state and is then placed between the tdi and tdo balls when the controller is moved to the shift-dr state. the extest, sample/preload and sample z in structions can be used to capture the contents of the io ring. the boundary scan order tables show the order in which the bits are connected. each bit corresponds to one of the bumps on the sram package. the msb of the register is connected to tdi, and the lsb is connected to tdo. identification (id) register the id register is loaded with a vendor-specific, 32-bit code during the capture-dr stat e when the idcode command is loaded in the instruction register . the idcode is hardwired into the sram and can be shifted out when the tap controller is in the shift-dr state. the id regi ster has a vendor code and other information described in the identification register definitions table. tap instruction set overview eight different instructions are possible with the three bit instruction register. al l combinations are listed in the instruction codes table. three of thes e instructions are listed as reserved and should not be used. the other five instructions are described in this section in detail. instructions are loaded into the tap controller during the shift-ir state when the instruction register is placed between tdi and tdo. during this state, instructions are shifted through the instruction register through the tdi and tdo balls. to execute the instruction once it is shifted in, the tap controller must be moved into the update-ir state. idcode the idcode instruction loads a vendor-specific, 32-bit code into the instruction register. it also places the instruction register between the tdi and tdo balls and shifts the idcode out of the device when the tap controller enters the shift-dr state. the idcode instruction is load ed into the instruction register upon power up or whenever the tap controller is given a test logic reset state. sample z the sample z instruction connects the boundary scan register between the tdi and tdo pins when the tap controller is in a shift-dr state. the sample z command puts the output bus into a high z state until the next command is given during the ?update ir? state. sample/preload sample/preload is a 1149.1 mandatory instruction. when the sample/preload instruct ions are loaded into the instruction register and the tap controller is in the capture-dr state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. the user must be aware that the tap controller clock can only operate at a frequency up to 20 mhz, while the sram clock operates more than an order of magnitude faster. because there is a large difference in the clock frequencies, it is possible that during the capture-dr state, an input or output undergoes a transition. the tap may then tr y to capture a signal while in transition (metastable state). this does not harm the device, but there is no guarantee as to the value that is captured. repeatable results may not be possible. to guarantee that the boundary scan register captures the correct value of a signal, the sram signal must be stabilized long enough to meet the tap controller?s capture setup plus hold times (t cs and t ch ). the sram clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a sample/preload instruction. if this is an issue, it is still possible to capture all othe r signals and simply ignore the value of the ck and ck captured in the boundary scan register. after the data is captured, it is possible to shift out the data by putting the tap into the shift-dr state. this places the boundary scan register between the tdi and tdo pins. preload places an initial data pattern at the latched parallel outputs of the boundary scan regist er cells prior to the selection of another boundary scan test operation. the shifting of data for the sample and preload phases can occur concurrently when require d?that is, while data captured is shifted out, the preloaded data can be shifted in. bypass when the bypass instruction is loaded in the instruction register and the tap is placed in a shift- dr state, the bypass register is placed between the tdi and tdo pins. the advantage of the bypass instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. [+] feedback
cy7c1441av33 CY7C1443AV33, cy7c1447av33 document number: 38-05357 rev. *i page 15 of 34 extest the extest instruction drives the preloaded data out through the system output pins. this in struction also connects the boundary scan register for serial access between the tdi and tdo in the shift-dr controller state. extest output bus tri-state ieee standard 1149.1 mandates t hat the tap controller be able to put the output bus in to a tri-state mode. the boundary scan register has a special bit located at bit #89 (for 165-ball fbga package) or bit #138 (for 209-ball fbga package). when this scan cell, called the ?extest output bus tri-state?, is latched into the preload register during the ?update-dr? state in the tap controller, it directly controls the state of the output (q-bus) pins , when the extest is entered as the current instruction. when high , it enables the output buffers to drive the output bus. when low, this bit places the output bus into a high z condition. this bit can be set by entering the sample/preload or extest command, and then shifting the desired bit into that cell, during the ?shift-dr? state. during ?update-dr?, the value loaded into that shift-register cell latches into the preload register. when the extest instruction is entered, this bit directly controls the output q-bus pins. note that this bit is pre-set high to enable the output when the device is powered-up, and also when the tap controller is in the ?test-logic-reset? state. reserved these instructions are not im plemented but are reserved for future use. do not use these instructions. tap timing t tl test clock (tck) 123456 t est mode select (tms) t th test data-out (tdo) t cyc test data-in (tdi) t tmsh t tmss t tdih t tdis t tdox t tdov dont care undefined [+] feedback
cy7c1441av33 CY7C1443AV33, cy7c1447av33 document number: 38-05357 rev. *i page 16 of 34 tap ac switchi ng characteristics over the operating range [9, 10] parameter description min max unit clock t tcyc tck clock cycle time 50 ? ns t tf tck clock frequency ? 20 mhz t th tck clock high time 20 ? ns t tl tck clock low time 20 ? ns output times t tdov tck clock low to tdo valid ? 10 ns t tdox tck clock low to tdo invalid 0 ? ns setup times t tmss tms setup to tck clock rise 5 ? ns t tdis tdi setup to tck clock rise 5 ? ns t cs capture setup to tck rise 5 ? ns hold times t tmsh tms hold after tck clock rise 5 ? ns t tdih tdi hold after clock rise 5 ? ns t ch capture hold after clock rise 5 ? ns notes 9. t cs and t ch refer to the setup and hold time requirements of latching data from the boundary scan register. 10. test conditions are specified using t he load in tap ac test conditions. t r /t f = 1 ns. [+] feedback
cy7c1441av33 CY7C1443AV33, cy7c1447av33 document number: 38-05357 rev. *i page 17 of 34 3.3 v tap ac test conditions input pulse levels ...............................................v ss to 3.3 v input rise and fall times ...................................................1 ns input timing reference levels .. ....................................... 1.5 v output reference levels ................................................ 1.5 v test load termination supply voltage ............................. 1.5 v 2.5 v tap ac test conditions input pulse levels ............ ................................... v ss to 2.5 v input rise and fall time ....................................................1 ns input timing reference levels ... .................................... 1.25 v output reference levels .............................................. 1.25 v test load termination supply vo ltage .......................... 1.25 v 3.3 v tap ac out put load equivalent t do 1.5v 20p f z=50 o 50 t do 1.25v 20p f z=50 o 50 (0 c < t a < +70 c; v dd = 3.135 v to 3.6 v unless otherwise noted) [11] parameter description conditions min max unit v oh1 output high voltage i oh = ?4.0 ma v ddq = 3.3 v 2.4 ? v i oh = ?1.0 ma v ddq = 2.5 v 2.0 ? v v oh2 output high voltage i oh = ?100 a v ddq = 3.3 v 2.9 ? v v ddq = 2.5 v 2.1 ? v v ol1 output low voltage i ol = 8.0 ma v ddq = 3.3 v ? 0.4 v i ol = 1.0 ma v ddq = 2.5 v ? 0.4 v v ol2 output low voltage i ol = 100 a v ddq = 3.3 v ? 0.2 v v ddq = 2.5 v ? 0.2 v v ih input high voltage v ddq = 3.3 v 2.0 v dd + 0.3 v v ddq = 2.5 v 1.7 v dd + 0.3 v v il input low voltage v ddq = 3.3 v ?0.3 0.8 v v ddq = 2.5 v ?0.3 0.7 v i x input load current gnd < v in < v ddq ?5 5 a note 11. all voltages referenced to v ss (gnd). [+] feedback
cy7c1441av33 CY7C1443AV33, cy7c1447av33 document number: 38-05357 rev. *i page 18 of 34 identification regi ster definitions instruction field cy7c1441av33 (1 m 36) CY7C1443AV33 (2 m 18) cy7c1447av33 (512 k 72) description revision number (31:29) 000 000 000 describes the version number. device depth (28:24) 01011 01011 01011 reserved for internal use architecture/memory type(23:18) [12] 000001 000001 000001 defines memory type and architecture bus width/density(17:12) 100111 010111 110111 defines width and density cypress jedec id code (11:1) 00000110100 00000110100 00000110100 allows unique identification of sram vendor. id register presence indicator (0) 1 1 1 indi cates the presence of an id register. scan register sizes register name bit size ( 36) bit size ( 18) bit size ( 18) instruction bypass 3 3 3 bypass 111 id 32 32 32 boundary scan order (165-ball fbga package) 89 89 ? boundary scan order (209-ball fbga package) ? ? 138 identification codes instruction code description extest 000 captures io ring contents. idcode 001 loads the id register with the vendor id code and places the register between tdi and tdo. this operation does not affect sram operations. sample z 010 captures io ring contents. places th e boundary scan register between tdi and tdo. forces all sram output drivers to a high z state. reserved 011 do not use: this instruct ion is reserved for future use. sample/preload 100 captures io ring contents. places the boundary scan register between tdi and tdo. does not affect sram operation. reserved 101 do not use: this instruct ion is reserved for future use. reserved 110 do not use: this instruct ion is reserved for future use. bypass 111 places the bypass register between tdi and tdo. this operation does not affect sram operations. note 12. bit #24 is ?1? in the id register definitions for both 2.5 v and 3.3 v ve rsions of this device. [+] feedback
cy7c1441av33 CY7C1443AV33, cy7c1447av33 document number: 38-05357 rev. *i page 19 of 34 165-ball fbga bo undary scan order [13, 14] cy7c1441av33 (1 m 36), CY7C1443AV33 (2 m 18) bit # ball id bit # ball id bit # ball id bit # ball id 1 n6 26 e11 51 a3 76 n1 2 n7 27 d11 52 a2 77 n2 3 n10 28 g10 53 b2 78 p1 4p11 29f10 54c2 79r1 5 p8 30 e10 55 b1 80 r2 6 r8 31 d10 56 a1 81 p3 7 r9 32 c11 57 c1 82 r3 8p9 33a11 58d1 83p2 9 p10 34 b11 59 e1 84 r4 10 r10 35 a10 60 f1 85 p4 11 r11 36 b10 61 g1 86 n5 12 h11 37 a9 62 d2 87 p6 13n11 38b9 63e2 88r6 14 m11 39 c10 64 f2 89 internal 15 l11 40 a8 65 g2 16 k11 41 b8 66 h1 17 j11 42 a7 67 h3 18 m10 43 b7 68 j1 19l10 44b6 69k1 20 k10 45 a6 70 l1 21 j10 46 b5 71 m1 22 h9 47 a5 72 j2 23h10 48a4 73k2 24 g11 49 b4 74 l2 25 f11 50 b3 75 m2 notes 13. balls which are nc (no connect) are preset low. 14. bit# 89 is preset high. [+] feedback
cy7c1441av33 CY7C1443AV33, cy7c1447av33 document number: 38-05357 rev. *i page 20 of 34 maximum ratings exceeding maximum ratings may shorten the useful life of the device. user guidelines are not tested. storage temperature .... ............ ............... ?65 ? c to +150 ? c ambient temperature with power applied ......................................... ?55 ?? c to +125 ? c supply voltage on v dd relative to gnd .....?0.3 v to +4.6 v supply voltage on v ddq relative to gnd .... ?0.3 v to +v dd dc voltage applied to outputs in tri-state ........................................?0.5 v to v ddq + 0.5 v dc input voltage ................................ ?0.5 v to v dd + 0.5 v current into outputs (low) .... .................................... 20 ma static discharge voltage ........................................ > 2001 v (per mil-std-883, method 3015) latch-up current ................................................... > 200 ma operating range range ambient temperature v dd v ddq commercial 0 c to +70 c 3.3 v ? ? 5% / + 10% 2.5 v ? 5% to v dd industrial ?40 c to +85 c electrical characteristics over the operating range [15, 16] dc electrical characteristics over the operating range parameter description test conditions min max unit v dd power supply voltage 3.135 3.6 v v ddq io supply voltage for 3.3 v io 3.135 v dd v for 2.5 v io 2.375 2.625 v v oh output high voltage for 3.3 v io, i oh = ?4.0 ma 2.4 ? v for 2.5 v io, i oh = ?1.0 ma 2.0 ? v v ol output low voltage for 3.3 v io, i ol = 8.0 ma ? 0.4 v for 2.5 v io, i ol = 1.0 ma ? 0.4 v v ih input high voltage [15] for 3.3 v io 2.0 v dd + 0.3 v v for 2.5 v io 1.7 v dd + 0.3 v v v il input low voltage [15] for 3.3 v io ?0.3 0.8 v for 2.5 v io ?0.3 0.7 v i x input leakage current except zz and mode gnd ? v i ? v ddq ?5 5 ? a input current of mode input = v ss ?30 ? ? a input = v dd ?5 ? a input current of zz input = v ss ?5 ? ? a input = v dd ?30 ? a i oz output leakage current gnd ? v i ? v ddq, output disabled ?5 5 ? a i dd v dd operating supply current v dd = max, i out = 0 ma, f = f max = 1/t cyc 7.5-ns cycle, 133 mhz ? 310 ma 10-ns cycle, 100 mhz ? 290 ma i sb1 automatic ce power down current?ttl inputs max v dd , device de selected, v in ? v ih or v in ? v il , f = f max , inputs switching all speeds ? 180 ma i sb2 automatic ce power down current?cmos inputs max v dd , device de selected, v in ? v dd ? 0.3 v or v in ? 0.3 v, f = 0, inputs static all speeds ? 120 ma notes 15. overshoot: v ih (ac) < v dd + 1.5 v (pulse width less than t cyc /2), undershoot: v il (ac) > ?2 v (pulse width less than t cyc /2). 16. t power-up : assumes a linear ramp from 0 v to v dd (min.) within 200 ms. during this time v ih < v dd and v ddq < v dd . [+] feedback
cy7c1441av33 CY7C1443AV33, cy7c1447av33 document number: 38-05357 rev. *i page 21 of 34 i sb3 automatic ce power down current?cmos inputs max v dd , device de selected, v in ? v ddq ? 0.3 v or v in ? 0.3 v, f = f max , inputs switching all speeds ? 180 ma i sb4 automatic ce power down current?ttl inputs max v dd , device de selected, v in ? v dd ? 0.3 v or v in ? 0.3 v, f = 0, inputs static all speeds ? 135 ma capacitance parameter [17] description test conditions 100-pin tqfp max 165-ball fbga max 209-ball fbga max unit c in input capacitance t a = 25 ? c, f = 1 mhz, v dd = 3.3 v, v ddq = 2.5 v 6.5 7 5 pf c clk clock input capacitance 3 7 5 pf c io input/output capacitance 5.5 6 7 pf thermal resistance parameter [17] description test conditions 100-pin tqfp package 165-ball fbga package 209-ball fbga package unit ? ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, per eia/jesd51. 25.21 20.8 25.31 ? c/w ? jc thermal resistance (junction to case) 2.28 3.2 4.48 ? c/w figure 2. ac test loads and waveforms electrical characteristics (continued) over the operating range [15, 16] dc electrical characteristics (continued) over the operating range parameter description test conditions min max unit output r = 317 ? r = 351 ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v t = 1.5 v 3.3 v all input pulses v ddq gnd 90% 10% 90% 10% ? 1 ns ? 1 ns (c) output r = 1667 ? r = 1538 ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v t = 1.25 v 2.5 v all input pulses v ddq gnd 90% 10% 90% 10% ? 1 ns ? 1 ns (c) 3.3 v io test load 2.5 v io test load note 17. tested initially and after any design or proc ess change that may affect these parameters. [+] feedback
cy7c1441av33 CY7C1443AV33, cy7c1447av33 document number: 38-05357 rev. *i page 22 of 34 switching characteristics over the operating range [18, 19] parameter description -133 -100 unit min max min max t power v dd (typical) to the first access [20] 1?1?ms clock t cyc clock cycle time 7.5 ? 10 ? ns t ch clock high 2.5 ? 3.0 ? ns t cl clock low 2.5 ? 3.0 ? ns output times t cdv data output valid after clk rise ? 6.5 ? 8.5 ns t doh data output hold af ter clk rise 2.5 ? 2.5 ? ns t clz clock to low z [21, 22, 23] 2.5?2.5?ns t chz clock to high z [21, 22, 23] ? 3.8 0 4.5 ns t oev oe low to output valid ? 3.0 ? 3.8 ns t oelz oe low to output low z [21, 22, 23] 0?0?ns t oehz oe high to output high z [21, 22, 23] ? 3.0 ? 4.0 ns setup times t as address setup before clk rise 1.5 ? 1.5 ? ns t ads adsp , adsc setup before clk rise 1.5 ? 1.5 ? ns t advs adv setup before clk rise 1.5 ? 1.5 ? ns t wes gw , bwe , bw x setup before clk rise 1.5 ? 1.5 ? ns t ds data input setup before clk rise 1.5 ? 1.5 ? ns t ces chip enable setup 1.5 ? 1.5 ? ns hold times t ah address hold after clk rise 0.5 ? 0.5 ? ns t adh adsp , adsc hold after clk rise 0.5 ? 0.5 ? ns t weh gw , bwe , bw x hold after clk rise 0.5 ? 0.5 ? ns t advh adv hold after clk rise 0.5 ? 0.5 ? ns t dh data input hold after clk rise 0.5 ? 0.5 ? ns t ceh chip enable hold after clk rise 0.5 ? 0.5 ? ns notes 18. timing reference level is 1.5 v when v ddq = 3.3 v and is 1.25 v when v ddq = 2.5 v. 19. test conditions shown in (a) of figure 2 on page 21 unless otherwise noted. 20. this part has a voltage regulator internally; t power is the time that the power must be supplied above v dd (minimum) initially, before a read or write operation can be initiated. 21. t chz , t clz ,t oelz , and t oehz are specified with ac test conditions shown in part (b) of figure 2 on page 21 . transition is measured 200 mv from steady-state voltage. 22. at any given voltage and temperature, t oehz is less than t oelz and t chz is less than t clz to eliminate bus contention between srams when sharing the same data bus. these specifications do not imply a bus contention condition, but reflect paramete rs guaranteed over worst case user condi tions. device is designed to achieve high z prior to low z under the same system conditions. 23. this parameter is sampled and not 100% tested. [+] feedback
cy7c1441av33 CY7C1443AV33, cy7c1447av33 document number: 38-05357 rev. *i page 23 of 34 timing diagrams figure 3. read cycle timing [24] . t cyc t cl clk t adh t ads address t ch t ah t as a1 t ceh t ces data out (q) high-z t clz t doh t cdv t oehz t cdv single read burst read t oev t oelz t chz burst wraps around to its initial state t advh t advs t weh t wes t adh t ads q(a2) q(a2 + 1) q(a2 + 2) q(a1) q(a2) q(a2 + 1) q(a2 + 2) q(a2 + 3) a2 adv suspends burst deselect cycle dont care undefined adsp adsc g w, bwe,bw x ce adv oe note 24. on this diagram, when ce is low: ce 1 is low, ce 2 is high and ce 3 is low. when ce is high: ce 1 is high or ce 2 is low or ce 3 is high. [+] feedback
cy7c1441av33 CY7C1443AV33, cy7c1447av33 document number: 38-05357 rev. *i page 24 of 34 figure 4. write cycle timing [25, 26] . timing diagrams (continued) t cyc t cl clk t adh t ads address t ch t ah t as a1 t ceh t ces high-z burst read burst write d(a2) d(a2 + 1) d(a2 + 1) d(a1) d(a3) d(a3 + 1) d(a3 + 2) d(a2 + 3) a2 a3 extended burst write d(a2 + 2) single write t adh t ads t adh t ads t oehz t advh t advs t weh t wes t dh t ds t weh t wes byte write signals are ignored for rst cycle when adsp initiates burst adsc extends burst adv suspends burst dont care undefined adsp adsc bwe, bw x gw ce adv oe data in (d) d ata out (q) notes 25. on this diagram, when ce is low: ce 1 is low, ce 2 is high and ce 3 is low. when ce is high: ce 1 is high or ce 2 is low or ce 3 is high. 26. full width write can be initiated by either gw low; or by gw high, bwe low and bw x low [+] feedback
cy7c1441av33 CY7C1443AV33, cy7c1447av33 document number: 38-05357 rev. *i page 25 of 34 figure 5. read/write cycle timing [27, 28, 29] . timing diagrams (continued) t cyc t cl clk t adh t ads address t ch t ah t as a2 t ceh t ces single write d(a3) a3 a4 burst read back-to-back reads high-z q(a2) q(a4) q(a4+1) q(a4+2) q(a4+3) t weh t wes t oehz t dh t ds t cdv t oelz a1 a5 a6 d(a5) d(a6) q(a1) back-to-back writes dont care undefined adsp adsc bwe, bw x ce adv oe data in (d) d ata out (q) note 27. on this diagram, when ce is low: ce 1 is low, ce 2 is high and ce 3 is low. when ce is high: ce 1 is high or ce 2 is low or ce 3 is high. 28. the data bus (q) remains in high z following a write cycle, unless a new read access is initiated by adsp or adsc . 29. gw is high. [+] feedback
cy7c1441av33 CY7C1443AV33, cy7c1447av33 document number: 38-05357 rev. *i page 26 of 34 figure 6. zz mode timing [30, 31] timing diagrams (continued) t zz i supply clk zz t zzrec a ll inputs (except zz) dont care i ddzz t zzi t rzzi outputs (q) high-z deselect or read only notes 30. device must be deselected when entering zz mode. see cycle de scriptions table for all possible signal conditions to deselect the device. 31. dqs are in high z when exiting zz sleep mode. [+] feedback
cy7c1441av33 CY7C1443AV33, cy7c1447av33 document number: 38-05357 rev. *i page 27 of 34 ordering information cypress offers other versions of this type of product in diff erent configurations and features. the following table contains on ly the list of parts that are currently available. for a complete listing of all options, visit the cypress website at www.cypress.com and refer to the product summary page at http://www.cypre ss.com/products , or contact your local sales representative. cypress maintains a worldwide network of offi ces, solution centers, manufacturer?s re presentatives and distributors. to find th e office closest to you, visit us at http://www.cypress.com/ go/datasheet/offices . ordering code definitions speed (mhz) ordering code package diagram part and package type 133 cy7c1441av33-133axc 51-85050 100-pin thin quad flat pack (14 20 1.4 mm) pb-free cy7c1441av33-133axi 51 -85050 100-pin thin quad flat pack (14 20 1.4 mm) pb-free cy7c1441av33-133bzi 51-85165 165-ball fine-pi tch ball grid array (15 17 1.4 mm) cy7c1441av33-133bzxi 51-85165 165-ball fine-pitch ball grid array (15 17 1.4 mm) pb-free temperature range: x = c or i c = commercial; i = industrial pb-free package type: xx = a or bz a = 100-pin tqfp bz = 165-ball fbga frequency range: 133 mhz v dd = 3.3 v process technology: ? 90 nm 1441 = ft, 1 mb 36 (36 mb) marketing code: 7c = srams company id: cy = cypress 7c 1441 v33 - x xx 133 cy a x [+] feedback
cy7c1441av33 CY7C1443AV33, cy7c1447av33 document number: 38-05357 rev. *i page 28 of 34 package diagrams figure 7. 100-pin tqfp (14 20 1.4 mm), 51-85050 51-85050 *d [+] feedback
cy7c1441av33 CY7C1443AV33, cy7c1447av33 document number: 38-05357 rev. *i page 29 of 34 figure 8. 165-ball fbga (15 17 1.4 mm), 51-85165 package diagrams (continued) 51-85165 *b [+] feedback
cy7c1441av33 CY7C1443AV33, cy7c1447av33 document number: 38-05357 rev. *i page 30 of 34 figure 9. 209-ball fbga (14 22 1.76 mm), 51-85167 package diagrams (continued) 51-85167 *a [+] feedback
cy7c1441av33 CY7C1443AV33, cy7c1447av33 document number: 38-05357 rev. *i page 31 of 34 acronyms document conventions units of measure acronym description cmos complementary metal oxide semiconductor fbga fine-pitch ball grid array i/o input/output jtag joint test action group lsb least significant bit msb most significant bit oe output enable sram static random access memory tap test access port tck test clock tdi test data-in tdo test data-out tms test mode select tqfp thin quad flat pack symbol unit of measure c degree celcius a micro amperes ma milli amperes mm milli meter ms milli seconds mhz mega hertz ns nano seconds ? ohms % percent pf pico farad vvolts wwatts [+] feedback
cy7c1441av33 CY7C1443AV33, cy7c1447av33 document number: 38-05357 rev. *i page 32 of 34 document history page document title: cy7c1441av33/cy7c1443av 33/cy7c1447av33, 36-mbit (1 m 36/2 m 18/512 k 72) flow-through sram document number: 38-05357 rev. ecn no. issue date orig. of change description of change ** 124459 03/06/03 cjm new data sheet *a 254910 see ecn syt part number changed from previous revision. new and old part number differ by the letter ?a? modified functional block diagrams modified switching waveforms added footnote #13 (32-bit vendor i.d code changed) added boundary scan information added i dd , i x and i sb values in the dc electrical characteristics added t power specifications in switching characteristics table removed 119 pbga package changed 165 fbga package from bb165c (15 x 17 x 1.20 mm) to bb165 (15 x 17 x 1.40 mm) changed 209-le ad pbga bg209 (14 x 22 x 2.20 mm) to bb209a (14 x 22 x 1.76 mm) *b 300131 see ecn syt removed 150 and 117 mhz speed bins changed ? ja and ? jc from tbd to 25.21 and 2.58 ? c/w respectively for tqfp package on pg # 21 added lead-free information for 100-pin tqfp, 165 fbga and 209 bga packages. added comment of ?lead-free bg and bz packages availability? below the ordering information *c 320813 see ecn syt changed h9 pin from v ssq to v ss on the pin configuration table for 209 fbga changed the test condition from v dd = min. to v dd = max for v ol in the electrical characteristics table. replaced the tbd?s for i dd , i sb1 , i sb2 , i sb3 and i sb4 to their respective values. replaced tbd?s for ? ja and ? jc to their respective values for 165 fbga and 209 fbga packages on the thermal resistance table. changed c in ,c clk and c io to 6.5, 3 and 5.5 pf from 5, 5 and 7 pf for tqfp package. removed ?lead-free bg and bz packages availability? comment below the ordering information *d 331551 see ecn syt modified address expansion ba lls in the pinouts for 165 fbga and 209 bga packages as per jedec standards and updated the pin definitions accordingly modified v ol, v oh test conditions replaced tbd to 100 ma for i ddzz changed c in , c clk and c io to 7, 7and 6 pf from 5, 5 and 7 pf for 165 fbga package. added industrial temperature grade changed i sb2 and i sb4 from 100 and 110 ma to 120 and 135 ma respectively updated the ordering information by shad ing and unshading mpns as per avail- ability [+] feedback
cy7c1441av33 CY7C1443AV33, cy7c1447av33 document number: 38-05357 rev. *i page 33 of 34 *e 417547 see ecn rxu converted from preliminary to final. changed address of cypress semiconductor corporation on page# 1 from ?3901 north first street? to ?198 champion court?. changed i x current value in mode from ?5 & 30 ? a to ?30 & 5 ? a respectively and also changed i x current value in zz from ?30 & 5 ? a to ?5 & 30 ? a respec- tively on page# 19. modified test condition in note# 8 from v ih < v dd to v ih ?? v dd. modified ?input load? to ?input leakage current except zz and mode? in the electrical characteristics table. replaced package name column with package diagram in the ordering information table. replaced package diagram of 51-85050 from *a to *b updated the ordering information. *f 473650 see ecn vkn added the maximum rating for supply voltage on v ddq relative to gnd. changed t th , t tl from 25 ns to 20 ns and t tdov from 5 ns to 10 ns in tap ac switching characteristics table. updated the ordering information table. *g 2447027 see ecn vkn/aesa corrected typo in the ordering information table corrected typo in the cy7c1447av33 ?s logic block diagram updated the x72 block diagram *h 2898501 03/24/2010 njy removed inactive part num bers from ordering information table; updated package diagrams. *i 3263570 05/23/2011 osn adeed ordering code definitions . updated package diagrams . added acronyms and units of measure . updated in new template. document history page (continued) document title: cy7c1441av33/cy7c1443av 33/cy7c1447av33, 36-mbit (1 m 36/2 m 18/512 k 72) flow-through sram document number: 38-05357 rev. ecn no. issue date orig. of change description of change [+] feedback
document number: 38-05357 rev. *i revised may 23, 2011 page 34 of 34 i486 is a trademark, and intel and pentium are registered trademarks of intel corporation. powerpc is a trademark of ibm corpor ation. all products and company names mentioned in this document may be the trademarks of their respective holders. cy7c1441av33 CY7C1443AV33, cy7c1447av33 ? cypress semiconductor corporation, 2003-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

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